1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly, to an integrated circuit capable of reconfiguration on the logic thereof.
2. Description of the Related Art
When a process to be executed is determined in advance, it is possible to realize a system that executes the process with high performance and at low power consumption by designing a dedicated LSI for the process. When executing a different process by changing the specification, however, it is necessary to redesign and remanufacture the LSI from scratch. Thus, dedicated LSIs possess very low specification change capability (capability of allowing specification change).
An example of configurations having high specification change capability is a configuration in which software is executed on a processor and the specification change is realized through rewriting the software. In this case, the specification change capability is very high. However, since the processor is configured such that general-purpose processes can be executed, the processor possesses high redundancy, resulting in low processing performance and high power consumption.
FPGAs (Field Programmable Gate Arrays) allow free reconfiguration of connections among logic devices by writing configuration data to a memory, so that change can be made for each gate. The FPGA possesses specification change capability, however, it is necessary to start over from RTL (Register Transfer Logic) design for specification change. Accordingly, though it is not necessary to remanufacture hardware as in dedicated LSIs, in terms of the logic design, labor equivalent to that required in changing the design of dedicated LSIs is required. In addition, because of the high redundancy of the hardware, the circuit size is increased to approximately ten times the size of a dedicated LSI, resulting in high cost and high power consumption.
Additionally, in SOCs (System on Chips), a processor and dedicated hardware are formed by the same LSI chip. The processor is used for controlling the dedicated hardware. The same problems of the above-described dedicated LSIs apply to the dedicated hardware.
Further, there is a configuration in which the FPGA and a processor are used together and dedicated hardware is controlled by the processor. In this configuration, regarding the FPGA, the same problems of the above-mentioned FPGA are applicable.
In addition, considering programming, even in a system having high specification change capability formed by a processor and software, when working out the design in a top-down manner, a lot of effort and time, that is, considerable work, load is required for the specification change of the software. In a top-down approach, the procedure is expressed by a flowchart. Thus, it is not easy to rewrite the flowchart and change the software. For instance, when a new process is added, it is necessary to add a conditional branch to a part of the existing program. This raises the need to further develop a process after the branch, in addition to merely adding the new process. When the software is changed repeatedly, the readability and ease of maintenance of the programs are degraded. Consequently, errors are increased and modification becomes impossible.
Additionally, in terms of programming, SOCs suffer from difficulty in assigning roles to software and hardware. In SOCs, a designer assigns processes to software and hardware based on his/her empirical knowledge in the initial stage of designing. Consequently, in many cases, the assignment of the processes is not optimized. Moreover, it is difficult to change the boundary between the software and hardware assignments later.
In other word, when assigning roles (processes) to software and hardware with a top-down approach, all the processes are considered in the initial stage of designing. Then, the processes causing heavy process load, which are empirically determined, are assigned to the hardware, and the processes causing light process load are assigned to the software. The system configuration obtained by such a designing method is not always optimized. It is not impossible to perform transition of processes from the hardware to the software later. In order to perform transition of processes from the software to the hardware, however, design change of the hardware and a manufacturing process in the factory are required.
The system called “Pleiades” (Hui Zhang, Vandana Prabhu, Varghese George, Marlene Wan, Martin Benes, Arthur Abnous, “A 1V Heterogenerous Reconfigurable Processor IC for Baseband Wireless Applications”, Proceedings of ISSCC2000) is proposed as a method for solving the problems as described above. The “Pleiades” includes a processor, a MAC (multiplier accumulator), an ALU (arithmetic logic unit), an AGU (address generating unit), a MEM (memory), an FPGA, and the like that are connected via a bus, and is designed to execute a single thread/process.
The “Pleiades” provides, in addition to a processor, a plurality of kinds of reconfigurable modules, each having a different granularity (the size of a reconfigurable unit), and dedicated hardware so as to offer an optimized configuration in terms of specification change capability, performance, and power consumption. The designing method, however, is in a top-down manner. Thus, processes to be transitioned from software operation to hardware (including a reconfigurable part) are determined, and optimization is performed by transitioning the processes to the hardware. Accordingly, the design change for the transition takes time.
In addition, the “Pleiades” performs signal processing by assigning a single process (or single thread) to each module. Thus, frequent data transfer is required among the modules, and the processing performance is limited by the resources in signal transmission channels among the modules. Considering such conditions from the viewpoint of hardware, in the “Pleiades”, each operation unit such as the MAC (multiplier accumulator) and the ALU (arithmetic logic unit), the FPGA, and the processor are provided in the same layer on the signal transmission channel. Accordingly, the amount of data transfer between the operation units, between the operation unit and the FPGA, or between the operation unit and the processor is increased, which causes degradation in the processing performance.